Generic BitBang Module of simavr AVR simulator.
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Generic BitBang Module of simavr AVR simulator.
- Features / Implementation Status
- easy buffer access with push() / pop() functions
- one input and one output pin (can be the same HW pin for I2C)
- Todo:
- one input and one output pin (can be the same HW pin for I2C)
- one clock pin which can be configured as input or output when the clock is output, the clock signal is generated with a configured frequency (master / slave mode)
- 2x 32-bit buffers (input / output) (allows start, stop bits for UART, etc.)
- on each read / write a callback is executed to notify the master module
SPI Module initialization and state structure.
reset bitbang sub-module
- Parameters
-
avr | avr attached to |
p | bitbang structure |
start bitbang transfer
buffers should be written / cleared in advanced timers and interrupts are connected
- Parameters
-
- Todo:
- test
stop bitbang transfer
timers and interrupts are disabled
- Parameters
-